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GS2986 multi-rate sdi reclocker with equalization & de-emphasis GS2986 1 of 41 GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 www.semtech.com features ? smpte 424m, smpte 292m and smpte 259m-c compliant ? supports dvb-asi at 270mb/s ? single supply operation at 3.3v or 2.5v ? 180mw typical power consumption (213mw with rco enabled) at 2.5v ? input signal equalization and output-signal de-emphasis settings to compensate for board-trace dielectric losses ? 4:1 input multiplexe r patented technology ? choice of dual reclocked data outputs or one reclocked data output and one clock output ? uses standard 27mhz crystal ? cascadable crystal buffer supports multiple reclockers using a single crystal ? differential inputs and outputs ? support dc coupling to industry-standard differential logic ? on-chip 100 differential data input/output termination ? selectable 400mvppd or 800mvppd output swing on each output ? seamless interface to other gennum products ? 4 wire spi host interface for device configuration and monitoring ? standard logic control and status signal levels ? auto and manual mode s for rate selection ? standards indication in auto mode ? lock detect output ? mute, bypass and autobypass functions ? sd/hd indication output to cont rol gs2978 or gs2988 dual slew-rate cable drivers ? operating temperature range: -40c to +85c ? small footprint qfn package (6mm x 6mm) ? pb-free and rohs compliant applications ? smpte 424m, smpte 292m and smpte 259m-c coaxial cable serial digital interfaces description the GS2986 is a multi-rate serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and retime the incoming vi deo data. it will recover the embedded clock signal and retime the data from a smpte 424m, smpte 292m, or smpte 259m-c co mpliant digital video signal. a serial host interface provides the ability to configure and monitor multiple gs2 986 devices in a dais y-chain configuration. adjustable input trace equalization (eq) for up to 40? of fr4 trace losses, and adjustable output de-emphasis (de) for up to 20? of fr4 trace losses, can be confi gured via the host interface. the GS2986 can operate in either auto or manual rate selection mode. in auto mode, the device will automatically detect and lock onto incoming smpte sdi data sign als at any supported rate. for single rate data systems, the GS2986 can be configured to operate in manual mode. in both modes, the device requires only one external crystal to set the vco frequency when not locked and provides adjustment free operation. the GS2986 accepts industry-standard differential input levels including lvpecl and cml. the differential data and clock outputs feature select able output swing via the host interface, ensuring compatibility with most industry-standard, terminated differential receivers. the GS2986 features dual differen tial outputs. the second output can be configured to emit either the recovered clock signal or the re-timed video data. this output can also be disabled to save power. in systems which require passing of non-smpte data rates, the GS2986 can be configured to eith er automatically or manually enter a bypass mode in order to pass the signal without reclocking. the GS2986 is pb-free, and the encapsulation compound does not contain halogenated flame retardant. this component and all homogeneous sub-components are rohs compliant.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 2 of 41 GS2986 functional block diagram revision history buffer control vco retimer spi ldo ldo xtal- cp_cap ddi0 ddi0 ddi1 ddi1 ddi2 ddi2 ddi3 ddi3 ddi_sel[1:0] los sdi/eq0_en sck/eq2_en sdo/eq1_en ddo0 ddo1/rco equalizer/ data mux xtal osc phase frequency detector phase detector selectable divide los detect charge pump selectable divide data buffer clock/ data buffer cs/eq3_en sd/hd ddo1_disable ddo0 ddo1/rco 1.8v xtal+ hif vdd_1p8 locked lf+ xtal_buf_out version ecr pcn date changes and/or modifications 3 158335 ? july 2012 remove d jumper from fi g ure 5-1: g s 2986 typi c al appli c ation c ir c uit 2 158129 ? may 2012 c orre c te d 4.15.3 se c tion to make it easier to follow an d c han g e d to s emte c h template. 1 153705 ? mar c h 2010 c onverte d to data s heet. up d ate d power num b ers in ta b le 2-1: d c ele c tri c al c hara c teristi c s . a dd e d ta b le 4-5: s u gg este d lo s threshol d s ettin g s . 0 152591 ? s eptem b er 2009 c onverte d to preliminary data s heet. up d ates to ele c tri c al c hara c teristi c s . up d ates to s e c tion 4.15 host interfa c e . b 151972 ? july 2009 a dd e d s e c tion 4.15 host interfa c e . up d ate d power num b ers in ta b le 2-1: d c ele c tri c al c hara c teristi c s an d loop ban d wi d th num b ers in ta b le 2-2: a c ele c tri c al c hara c teristi c s . a dd e d ta b le 1-2: g s 2986 default s tart-up s ettin g s an d fi g ure 4-2: de-emphasis waveform . a 151668 ? april 2009 new d o c ument.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 3 of 41 contents features....................................................................................................................... ..........................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 revision history ............................................................................................................... ..................................2 1. pin out..................................................................................................................... ..........................................5 1.1 pin assignment ............................................................................................................ ......................5 1.2 pin descriptions .......................................................................................................... ......................6 1.3 default start-up settings ................................................................................................. ...............8 2. electrical characteristics .................................................................................................. ..........................9 2.1 absolute maximum ratings .................................................................................................. ........9 2.2 dc electrical characteristics ...... ....................................................................................... ...........9 2.3 ac electrical characterist ics ............................................................................................. ........ 10 3. input/output circuits ....................................................................................................... ........................ 13 4. detailed description........................................................................................................ .......................... 17 4.1 serial data input ......................................................................................................... ................... 17 4.2 modes of operation ........................................................................................................ .............. 17 4.3 input trace equalization .................................................................................................. ........... 17 4.4 4:1 input mux ............................................................................................................. ..................... 18 4.5 crystal buffer ............................................................................................................ ...................... 19 4.6 los (loss of signal) detection ............................................................................................ ...... 19 4.7 serial digital reclocker .................................................................................................. ............. 20 4.8 lock detection ............................................................................................................ .................... 20 4.8.1 lock detect and asynchronous lock ......................................................................... 21 4.9 serial data output ........................................................................................................ ................. 21 4.9.1 output signal interface levels...................................................................................... 21 4.9.2 adjustable output swing................................................................................................ 21 4.9.3 output de-emphasis ....................................................................................................... .21 4.10 automatic and manual data rate selection ...................................................................... 22 4.11 sd/hd indication ................................................................................................................... ..... 23 4.12 bypass mode .............................................................................................................. ................... 23 4.13 dvb-asi .................................................................................................................. ....................... 24 4.14 output mute and data/clock output selection ............................................................... 24 4.15 host interface ........................................................................................................... .................... 24 4.15.1 introduction ............................................................................................................ .......... 24 4.15.2 legacy mode & start-up................................................................................................ 25 4.15.3 host interface mode & start-up.................................................................................. 25 4.15.4 clock & data timing..................................................................................................... .. 25 4.15.5 single device operation ............................................................................................... 25 4.15.6 write operation - single device ................................................................................ 26 4.15.7 read operation - single device ................................................................................. 27 4.15.8 daisy chain operation.................................................................................................. 2 9 4.15.9 read & write operation - daisy chained devices .............................................. 30 4.15.10 writing to all devices ................................................................................................. .30 4.15.11 writing to a single device in the chain ................................................................ 31
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 4 of 41 4.15.12 reading from all devices ........................................................................................... 31 4.15.13 reading from a single device in the chain.......................................................... 32 4.15.14 host register map...................................................................................................... ... 33 4.16 device power-up .......................................................................................................... ............... 36 4.17 standby .................................................................................................................. ......................... 36 5. typical application circuit ......... ........................................................................................ .................... 37 6. package and ordering information............................................................................................ .......... 38 6.1 package dimensions ........................................................................................................ ............. 38 6.2 recommended pcb footprint .. ........... ........... ........... ........... ........... ........... ........... ........... ....... .. 39 6.3 packaging data ............................................................................................................ ................... 39 6.4 marking diagram ........................................................................................................... ................ 40 6.5 solder reflow profile ..................................................................................................... ............... 40 6.6 ordering information ...................................................................................................... ............. 41
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 5 of 41 1. pin out 1.1 pin assignment fi g ure 1-1: g s 2986 pin out 1 2 3 4 rsvd 5 6 7 8 9 10 11 12 13 14 15 1 6 ddi0 ddi1 ddi0 ddi1 g round pad (bottom of package) g s298 6 40-pin qfn (top view) xtal_buf_out xtal+ xtal- sck/eq2_en sdo/eq1_en sdi/eq0_en vee_cp vcc_cp lf+ cp_cap cs/eq3_en vee_ddo0 vcc_ddo0 ddo0 vee_ddo1 vcc_ddo1 ddo1/rco ddi_sel0 vee_vco vdd_1p8 locked los vdd_di g vss_di g ddo0 ddo1/rco sd/hd 17 18 19 20 21 22 23 24 25 2 6 27 28 29 30 31 32 33 34 35 3 6 37 38 39 40 ddi2 ddi2 ddi3 ddi3 ddo1_disable vcc_vco hif ddi_sel1
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 6 of 41 1.2 pin descriptions table 1-1: GS2986 pin descriptions pin number name ty p e description 1 c p_ c ap power external c apa c itor for internal ldo re g ulator supplyin g the c har g e pump c ir c uit. 2, 4 ddi0, ddi0 input s erial di g ital differential input 0. 3hif lo g i c input host interfa c e sele c tion pin. a c tive-low input. s ee s e c tion 4.15.1 . 5, 6 ddi1, ddi1 input s erial di g ital differential input 1. 7, 8 ddi2, ddi2 input s erial di g ital differential input 2. 9, 10 ddi3, ddi3 input s erial di g ital differential input 3. 11 r s vd reserve d reserve d pin. do not c onne c t to this pin. 12, 13 ddi_ s el[0:1] lo g i c input s ele c ts one of four serial d i g ital input si g nals for pro c essin g . s ee s e c tion 4.4 . 14 v cc _v c opower most positive power supply c onne c tion for the internal v c o se c tion. c onne c t to a 3.3v supply with a 422 resistor, or to a 2.5v supply with a 267 resistor. 15 vee_v c opower most ne g ative power supply c onne c tion for the internal v c o se c tion. c onne c t to gnd. 16 vdd_1p8 power external c apa c itor for internal 1.8v d i g ital supply. 17 lo c ked output lo c k dete c t status si g nal. high when the pll is lo c ke d . 18 lo s output loss of s i g nal status. high when the input si g nal is invali d . 19 vdd_dig power most positive power supply c onne c tion for the d i g ital c ore. c onne c t to 3.3v or 2.5v. 20 v ss _dig power most ne g ative power supply for the d i g ital c ore. c onne c t to gnd. 21 s d/hd output this si g nal will b e low for all rates other than 270m b /s. this si g nal is high for 270m b /s. 22 ddo1_di s able lo g i c input disa b les the ddo1/r c o an d ddo1 /r c o outputs when low. s ee s e c tion 4.14 . 23, 24 ddo1/r c o , ddo1/r c o output differential serial c lo c k or d ata outputs. 25 v cc _ddo1 power most positive power supply c onne c tion for the ddo1/ddo1 output d river. c onne c t to 3.3v or 2.5v. 26 vee_ddo1 power most ne g ative power supply c onne c tion for the ddo1/ddo1 output d river. c onne c t to gnd. 27, 28 ddo0 , ddo0 output differential s erial di g ital outputs.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 7 of 41 29 v cc _ddo0 power most positive power supply c onne c tion for the ddo0/ddo0 output d river. c onne c t to 3.3v or 2.5v. 30 vee_ddo0 power most ne g ative power supply c onne c tion for the ddo0/ddo0 output d river. c onne c t to gnd. 31 xtal_buf_out output buffere d output of the referen c e os c illator. 32 xtal+ output referen c e c rystal output. 33 xtal- input referen c e c rystal input. 34 cs /eq3_en input/lo g i c input in host mo d e (hif set low): c hip sele c t input for s pi serial host interfa c e. a c tive-low input. in non-host mo d e (hif set high): tra c e e q ualization on/off pin for s erial di g ital differential input 3. a c tive-hi g h input. 35 sc k/eq2_en input/lo g i c input in host mo d e (hif set low): burst-mo d e c lo c k input for s pi serial host interfa c e. in non-host mo d e (hif set high): tra c e e q ualization on/off pin for s erial di g ital differential input 2. a c tive-hi g h input. 36 s do/eq1_en input/lo g i c input in host mo d e (hif set low): s erial d i g ital d ata output for s pi serial host interfa c e. a c tive-hi g h output. in non-host mo d e (hif set high): tra c e e q ualization on/off pin for s erial di g ital differential input 1. a c tive-hi g h input. 37 s di/eq0_en input/lo g i c input in host mo d e (hif set low): s erial d i g ital d ata input for s pi serial host interfa c e. a c tive-hi g h input. in non-host mo d e (hif set high): tra c e e q ualization on/off pin for s erial di g ital differential input 0. a c tive-hi g h input. 38 vee_ c p power most ne g ative power supply c onne c tion for the internal c har g e pump. c onne c t to gnd. 39 v cc _ c ppower most positive power supply c onne c tion for the internal c har g e pump. c onne c t to 3.3v or 2.5v 40 lf+ passive loop filter c apa c itor c onne c tion. ( c lf = 47nf). c onne c t as shown in typi c al appli c ation c ir c uit on pa g e 37 . ? c enter pa d ? groun d pa d on b ottom of pa c ka g e. c onne c t to gnd. table 1-1: GS2986 pin descriptions (continued) pin number name ty p e description
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 8 of 41 1.3 default start-up settings the GS2986 has some functions that are not acce ssible via direct pin control, and are only accessible through the host interface registers. these functions have an internal pull-up or pull-down resistor that sets the default logic level or start-up state, if it is not already set by a pin. if the user wishes to override these logic levels, the associated bit should be programmed within the pin_or_1 register (pin override register) at address 0x0c. the logic values within the pin_or_1 register become active when the user sets the pin override enable bit to high within that same register. table 1-2 shows: 1. the default logic state set by the internal pull-up or pull-down resistors. 2. the default values within the pin override register upon reset. more details are given in section 4.15 . table 1-2: GS2986 de fault start-up settings name description default state set by internal resistors default state within the pin override register bypa ss bypasses the re c lo c ker sta g e when set high. 0 0 autobypa ss when set high, this b it automati c ally b ypasses the re c lo c ker sta g e when the pll is not lo c ke d to a supporte d rate. 00 auto/man when set high, the stan d ar d is automati c ally d ete c te d from the input d ata rate. 10 ss 0, ss 1 when auto/man is set high, ss [1:0] are outputs d isplayin g the d ata rate to whi c h the pll has lo c ke d . therefore, the b its will not have a d efault start-up value. none 0:0 kbb c ontrols the loop b an d wi d th of the pll. floatin g groun d data_mute mutes the ddo0/ddo0 an d ddo1/ddo1 (if d ata is sele c te d ) outputs when low. 10 data/ c lo c k high = data low = c lo c k 00 de_en de-emphasis on/off pin for serial d i g ital output. high = d e-emphasis on low = d e-emphasis off 00
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 9 of 41 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value s upply volta g e -0.5 to +3.6v d c input e s d volta g e 4kv s tora g e temperature ran g e -50o c < t a < 125o c operatin g temperature ran g e -40o c to 85o c input volta g e ran g e -0.3 to (v cc + 0.3) v d c s ol d er reflow temperature 260o c table 2-1: dc electrical characteristics parameter symbol conditions min ty p max units s upply volta g e vdd 3.3v 3.135 3.3 3.465 v 2.5v 2.375 2.5 2.625 v power (ddo1/r c o d isa b le d , minimum output swin g ) p vdd = 3.3v ? 250 325 mw vdd = 2.5v ? 180 235 mw power (ddo1/r c o ena b le d , minimum output swin g ) vdd = 3.3v ? 290 390 mw vdd = 2.5v ? 210 275 mw power in power- d own mo d e vdd = 3.3v ? 48 60 mw vdd = 2.5v ? 30 40 mw s erial input termination ? differential 80 100 120 s erial output termination ? differential 80 100 120 s erial input c ommon mo d e volta g e ?? 1.6 ? vdd v s erial output c ommon mo d e volta g e ?? ? v cc - ( vod /2) ? v vil (2.5v operation) ? vout vol, max -0.3 ? 0.7 v vil (3.3v operation) vout vol, max -0.3 ? 0.8 v vih (2.5v operation) ? vout voh, min 1.7 ? vdd +0.3 v vih (3.3v operation) vout voh, min 2 ? vdd +0.3 v iin ? vin = 0v or vin = vdd ? +/-10 +/-20 a
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 10 of 41 2.3 ac electrical characteristics vol (2.5v operation) ? vdd = min, iol = 100 a ?? 0.2 v vol (3.3v operation) vdd = min, iol = 100 a ?? 0.2 v voh (2.5v operation) ? vdd = min, ioh = -100 a2.1 ?? v voh (3.3v operation) vdd = min, ioh = -100 avdd -0.4 ?? v hysteresis volta g e ( s pi inputs) note: g uarantee d b y simulation. ? 2.5v operation ? 350 ? mv 3.3v operation ? 350 ? mv table 2-1: dc electrical characteristics (continued) parameter symbol conditions min ty p max units table 2-2: ac electrical characteristics parameter symbol conditions min ty p max units notes s erial input data rate (for re c lo c kin g ) dr s do ? 0.27 ? 2.97 g b /s ? s erial input data rate ( b ypass) ? d c ? 2.97 g b /s ? s pi operatin g s pee d ?? ?? 10 mhz ? input volta g e s win g v s di s et atten_en = 1 for v s di>1v pp 100 ? 2000 mv p-p d ? output volta g e s win g vod d efault 300 400 500 mv p-p d ? see driver_1 re g ister (0x01) a dd resses 8 & 9 in 4.15.14 host re g ister map . 600 800 1000 mv p-p d ? input tra c e e q ualization ? low re c ommen d e d settin g for 0 to 10 in c hes of fr4 ? med re c ommen d e d settin g for 10 to 20 in c hes of fr4 ? high re c ommen d e d settin g for >20 in c hes of fr4 ?
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 11 of 41 output de-emphasis ? off - 0 ? 0 ? d b ? on - 0 ? 0 ? d b ? on - 1 ? 0.7 ? d b ? on - 2 ? 1.3 ? d b ? on - 3 ? 2 ? d b ? on - 4 ? 2.6 ? d b ? on - 5 ? 3.3 ? d b ? on - 6 ? 4 ? d b ? on - 7 ? 4.7 ? d b ? input jitter toleran c e ? s q uare-wave mo d ulate d jitter 0.8 ?? ui ? loop ban d wi d th bw loop (270m b /s) kbb = v cc ? 170 ? khz ? kbb = float ? 340 ? khz ? kbb = gnd ? 680 ? khz ? bw loop (1485m b /s) kbb = v cc ? 0.875 ? mhz ? kbb = float ? 1.75 ? mhz ? kbb = gnd ? 3.5 ? mhz ? bw loop (2970m b /s) kbb = v cc ? 1.75 ? mhz ? kbb = float ? 3.5 ? mhz ? kbb = gnd ? 7.0 ? mhz ? pll lo c k time (asyn c hronous) t alo c k ?? 0.5 1 ms ? pll lo c k time (syn c hronous) t slo c k c lf = 47nf, s d/hd = 0 ? 0.5 4 s ? c lf = 47nf, s d/hd = 1 ? 510 s ? s erial data output jitter intrinsi c (ddo0) t oj(270mb/s) kbb = float prn 2^23-1 test pattern ? 0.01 ? ui ? t oj(1485mb/s) kbb = float prn 2^23-1 test pattern ? 0.03 ? ui ? t oj(2970mb/s) kbb = float prn 2^23-1 test pattern ? 0.05 ? ui ? output rise/fall time tr/f 20% to 80% (400mv swin g ) ? 65 ? ps ? 20% to 80% (800mv swin g ) ? 80 ? ps ? output rise/fall time mismat c h ?? ?? 15 ps ? table 2-2: ac electrical characteristics (continued) parameter symbol conditions min ty p max units notes
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 12 of 41 eye c ross s hift ? per c enta g e of si g nal amplitu d e ?? 5% ? power s upply noise reje c tion ? 50 - 100hz ? 100 ? mv p-p ? 100hz - 10mhz ? 40 ? mv p-p ? 10mhz - 1.485ghz ? 10 ? mv p-p ? table 2-2: ac electrical characteristics (continued) parameter symbol conditions min ty p max units notes
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 13 of 41 3. input/output circuits fi g ure 3-1: hi g h-spee d inputs (ddi0, ddi0 , ddi1, ddi1 , ddi2, ddi2 , ddi3, ddi3 ) fi g ure 3-2: low-spee d input with weak internal pull-up ( hif , ddo1_di s able ) ddi ddi 25 25 25 25 5.55k 12.9 6 k vcc vcc vcc in vref 1.4k vcc vcc 2.5a
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 14 of 41 fi g ure 3-3: low-spee d input with weak internal pull- d own (ddi_ s el0, ddi_ s el1) fi g ure 3-4: low-spee d outputs (lo c ked, lo s , s d/ hd ) fi g ure 3-5: hi g h-spee d outputs ( ddo1 / r c o , ddo1/r c o, ddo0 , ddo0) in vref 1.4k vcc vcc 2.5a vcc out vcc 972 ddo vcc 50 50 vcc vcc ddo
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 15 of 41 fi g ure 3-6: c rystal buffere d output (xtal_buf_out) fi g ure 3-7: hi g h-spee d c rystal os c illator i/o (xtal-, xtal+) fi g ure 3-8: s pi inputs/eq c trl ( cs /eq3_en, sc k/eq2_en, s di/eq0_en) vcc xtal_buff_out vcc vcc vcc xtal- vcc en en vcc xtal+ 24 6 vcc vcc 2.5a
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 16 of 41 fi g ure 3-9: s pi output/eq c ontrol ( s do/eq1_en) sdo vref 1.4k vcc vcc vcc 2.5a tgate spi sdo tri-state logic
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 17 of 41 4. detailed description the GS2986 is a multi-standa rd reclocker for serial digital sd tv signals operating at 270mb/s, and hdtv signals operating at 1.485gb/s , 1.485/1.001gb/s, 2.97gb/s and 2.97/1.001gb/s. 4.1 serial data input the GS2986 features four di fferential input buffers. the serial data input signal is connected to the ddi0/ddi0 , ddi1/ddi1 , ddi2/ddi2 and ddi3/ddi3 input pins of the device. input signals can be single-ended or differential, dc or ac-coupled. the input circuit is self-biasing, to allow for simple ac or dc-coupling of input signals to the device. 4.2 modes of operation the GS2986 has two modes of op eration: legacy mode (hif = high) and spi mode (hif = low). in legacy mode, chip functions are controlled via pins only, and offers limited control of input equalization. in spi mode, access is gained to extended digital controls like: bypass, autobypass, auto/manual selection, control status inputs or outputs, changes to kbb settings, additional eq and de settings as well as access to additional features such as los adjustment, polarity invert, auto-mute, etc. 4.3 input trace equalization the GS2986 features adjustable tr ace equalization to compensate for pcb tr ace dielectric losses at 1.5ghz. the trace equalization has three peak-gain settings. the maximum peak gain value is optimized for compensating the high-frequency losses associated with 25 inches of 5-mil stripline in fr4 material. for boards with different striplines or materials, users can experiment to find the eq setting which optimizes their system performance. these settings are accessible via the serial host interface. each serial digital input; ddi, ddi includes a pin eqn_en to turn its trace equalizer on or off. when a pin eqn_en is tied low or left unconnected, the trace equalization for input n is set to low. when an eqn_en pin is tied high, and input n is selected, the trace equalization for input n is set to medium.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 18 of 41 the default peak-gain setting upon power-up is optimized for compensating the high-frequency losses associated with approx imately 10 inches of 5- mil stripline in fr4 material. the eqn_en pins are multiplexed with the serial host interface pins when pin hif is tied high, as shown in table 4-2 : 4.4 4:1 input mux the GS2986 incorporates a 4:1 in put mux, which allows the co nnection of four independent streams of video/data. there are four differential inputs (ddi[3:0] / ddi[3:0] ). the active channel can be selected via the ddi_sel[1:0] pins as shown in table 4-3 . the ddi_sel pins include internal pulldowns whic h pull the input voltage low if either pin is unconnected. active circuitry associated with the input buffers and trace eq can only be turned on for the selected input. inputs which are not selected have their input buffers and trace eqs turned off to save power. unused inputs can be either left floating, or tied to vcc. table 4-1: input trace equalization operation eqn_en setting trace equalization low low high me d ium table 4-2: eqn_en pins multiplexed pin function s di/eq0_en a c tive-hi g h lo g i c input to ena b le tra c e-e q ualization for hi g h-spee d input c hannel 0. s do/eq1_en a c tive-hi g h lo g i c input to ena b le tra c e-e q ualization for hi g h-spee d input c hannel 1. sc k/eq2_en a c tive-hi g h lo g i c input to ena b le tra c e-e q ualization for hi g h-spee d input c hannel 2. cs /eq3_en a c tive-hi g h lo g i c input to ena b le tra c e-e q ualization for hi g h-spee d input c hannel 3. table 4-3: input selection table ddi_sel[1:0] selected input 00 ddi0 01 ddi1 10 ddi2 11 ddi3
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 19 of 41 4.5 crystal buffer the GS2986 features a crystal buffer supporti ng a gennum recommended external 27mhz crystal. the GS2986 requires an external 27mhz refe rence clock for correct operation. this reference clock is generated by connecting a crystal to the xtal- and xtal+ pins of the device. alternately, a 27mhz external clock source can be connected to the xtal- pin of the device, while the xtal+ pin should be left floating. 4.6 los (loss of signal) detection the los (loss of signal) status pin is an active-h igh output that indicates when the serial digital input signal selected at the 4:1 input mux is invalid. in order for this output to be asserted, transitions must not be present for a period of t la = 5 - 10 s. after this output has been asserted, los will de-assert within t ld = 0 - 5 s after the appearance of a tran sition at the ddix input. see figure 4-1 . this signal is high (signal lost), when the number of data edges within a window is below a defined threshold. the output is automatically muted when los is detected. this signal is low (signal vali d), when the number of data ed ges within a window is above a defined threshold. see table 4-4 . the los function is operational for all operating modes of the device. fi g ure 4-1: lo s s i g nal timin g the los detector has two major modes. in legacy mode, a simple edge-based detector is used to monitor the received signal at the output of the data slicer. since the incoming signal has undergone considerable gain by this point, the legacy detector can be more susceptible to false de-assertion of los for unused channels which experience significant cross-talk from adjacent active channels. table 4-4: los operation los signal high invali d low vali d data lo s t la t ld
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 20 of 41 the new los detector uses a measure of both signal amplitude and duration to minimize false detection of the impulse like signals that are characteristic of cross-talk. in this mode, the signal is tapped off at the output of the equalizer stage, prior to the high gain buffers. the threshold setting within the detector can be adjusted to increase or decrease its sensitivity. gennum recommends using the least sensitive threshold level. this provides the most margin against false de-assertion of los. the los mode can be selected by using the host interface, in regist er top_1 (address 0x02). 4.7 serial digital reclocker the output of the equalizer is fed to the reclocker. the function of the reclocker is to re-time the input signal and to generate system clocks. the reclocker operates at three frequencies; 2.97gb/s, 1.485gb/s and 270mb/s, and provides a minimum input jitter tolerance of 0.8ui to square-wave-modulated jitter at these rates. when there is no serial input signal, the inte rnal clock maintains a frequency close to the expected incoming data rate by locking to the external reference crystal. 4.8 lock detection the lock detect block indicates, via the acti ve-high locked signal, when the device has achieved lock to the incoming data stream. the lock logic within the GS2986 includes a syst em that monitors the frequency and the phase of the incoming data, as well as a monitor to detect harmonic lock. the locked output signal is also available via the host interface. table 4-5: suggested los threshold settings los detection method select los threshold adjust input s i g nal amplitu d e >250mv 0x1 0x0 200mv to 250mv 0x1 0x1 150mv to 200mv 0x1 0x2 <150mv 0x1 or 0x0 0x3 table 4-6: lock operation locked status high lo c ke d low not lo c ke d
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 21 of 41 4.8.1 lock detect and asynchronous lock the reference crystal is used to assist the pll in achieving short lock time. the lock detection algorithm is a continuous process, which begins at device power up or after a system reset, and continues until the device is powered down. the asynchronous lock time is defined as the time it takes the device to lock when a video signal is first applied to the serial digital inputs, or when the digital video signal rate changes. the synchronous lock time is defined as the time it takes the device to lock to a signal which has been momentarily interrupted. 4.9 serial data output the GS2986 features two current-mo de differential output drivers, each capable of driving a maximum of 800mv pp , differential, into an external 100 differential load. each of the GS2986's output buffers include two on-chip, 50 termination resistors. 4.9.1 output signal interface levels the serial digital outputs of the GS2986 are co mpatible when dc-coupled with all gennum serial digital interface products that feature a differential lvpecl or cml receiver designed for sdi applications and operate from 3.3v or 2.5v supplies. this includes but is not limited to: gs2978, gs2988, and gs2989. the serial digital data inputs are also compatible when dc-coupled with lvpecl or cml differential outputs from crosspoint switches wh ich operate from 3.3v or 2.5v supplies. this includes but is not limited to: gs 2974a, gs2974b, and gs2984 equalizers. 4.9.2 adjustable output swing it is possible, via the host interface, to force the output swing to 400mv pp or 800mv pp differential, when the outputs are terminated with 50 loads. the default output swing upon power-up is 400mv pp differential. 4.9.3 output de-emphasis the GS2986 features adjustable ou tput de-emphasis to compensa te for pcb trace dielectric losses. the output de-emphasis has eight settings, evenly distributed from a minimum of 0db (output de-emphasis off) to a peak de-emphasis setting that is optimized for compensating the high-frequency losses associated with approx imately 20 inches of 5-mil stripline in fr4 material. these settings are accessible via the serial host interface. the action of the de-emphasis settings is to attenuate the trailing edge of the output data waveform relative to the output swings set through the host interface. de-emphasis is turned off when in bypass mode. the default de-emphasis setting upon power-up is 0db (off). note: changing the de-emphasis setting will vary both v1 & v2 (see figure 4-2 ).
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 22 of 41 fi g ure 4-2: de-emphasis waveform 4.10 automatic and manual data rate selection the GS2986 can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. the default configuration is auto mode. this can be changed via the host interface. in auto mode, the ss[1:0] registers become read only, and the bit pattern indicates the data rate at which the pll is currently locked to (or prev iously locked to). the search algorithm cycles through the data rates and starts over if that data rate is not found (see figure 4-3 ). a ?search algorithm? cycles through the supported data rates until lock is achieved, as shown in figure 4-3 below. fi g ure 4-3: g s 2986 automati c mo d e s ear c h al g orithm in manual mode, the ss[1:0] registers become re ad or write pins become inputs and the data rate can be programmed. in this mode, the search algorithm is disabled and the GS2986's pll v1 v2 -v1 -v2 tx signal after de-emphasis 11110000 pattern 2 6 8 2 6 9 270 271 272 273 274 275 ui volts -0. 6 -0.4 -0.2 0 0.2 0.4 0. 6 de-emphasis (db) =20 log (v1/v2) power up 270mb/s 1485mb/s 2970mb/s *note: the search algorithm does not necessarily begin with 270mb/s.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 23 of 41 will only lock to the data rate selected in accordance with table 4-7 . 4.11 sd/ hd indication the sd/hd signal indicates the output data rate of the device and can be connected to the sd/hd input pin of dual slew rate cable drivers such as the gs2988. when this signal is high, the da ta rate is 270mb/s. th is signal is low for all other data rates. this signal is also low when the device is operating in bypass mode (auto-bypass and user-bypass). the sd/hd signal is low when the device is not locked. 4.12 bypass mode in bypass mode, the GS2986 passes the data at the inputs, direct ly to the output. there are two register bits that control the bypass function: bypass and autobypass. the bypass bit is an active-high signal which fo rces the GS2986 into bypa ss mode for as long as the bit is asserted high. the autobypass bit is an active-high signal that places the GS2986 in to bypass mode only when the pll has not locked to a data rate. note that if bypass is high, this will override the autoby pass functionality. when the GS2986's pll is not locked and bypa ss = low and autobypass = low, the serial digital output ddo/ddo will produce invalid data. table 4-7: data rate indi cation/selecti on bit pattern ss[1:0] data rate (mb/s) 0 reserve d 1270 2 1485 or 1485/1.001 3 2970 or 2970/1.001 table 4-8: bypass modes bypass autobypass device operation high x bypass mo d e low high bypass mo d e if the pll has not lo c ke d to a d ata rate low low power-up d efault. normal operation, part always tries to lo c k to the in c omin g d ata stream.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 24 of 41 the autobypass function will bypass unsupported (non-reclocked) smpte sdi signal rates without producing bi t errors: 143mb/s, 177m b/s, 360mb/s, 540mb/s. 4.13 dvb-asi the GS2986 also reclocks dvb-as i signals at 270mb/s. in au to mode, the device will automatically lock to the incoming 270mb/s signal. in manual mode, the ss[1:0] pins must be set to 01 (270mb/s) to ensu re proper operation. 4.14 output mute and data /clock output selection the data_mute register is provided to allow muting of the serial digital data output. setting data_mute = low will force the seri al digital outputs ddo/ddo to mute (statically latch high) under all conditions and operating modes. the ddo1_disable pin is provided to allow the second data/clock output to be powered down. when ddo1_disable is set low, the serial digital clock outputs ddo1/ rco and ddo1/rco are muted and the driver is powered-down. the data/clock register is provided to allow the second output to emit a copy of the reclocked serial data or the recovered clock. in legacy mode, the de fault is data output. 4.15 host interface 4.15.1 introduction the GS2986 offers a serial peri pheral interface (spi) to ac cess advanced features and programmability. the polarity of the hif pin tells the GS2986 whether or not the host interface is active (hif = 0) or in legacy mode (hif = 1). using the host interface, it is possible to override the control pin settings, and such settings will persist until the device has been powered-down and/or reset. the host interface is capable of table 4-9: configuration of GS2986 output drivers and mute/disable pins data_mute ddo1_disable data/clock ddo0 ddo1/rco 110data c lo c k 1 1 1 data data 010mute c lo c k 0 1 1 mute mute 10xdatapower d own 00xmutepower d own
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 25 of 41 reading hard-wired pin configuration, pin override settings and the values of all status monitoring pins. there is an optional 3-state feature availabl e in the control status registers (csr) that puts the spi sdo to high-impedance when it?s not being used (register: top_1, bit: 2). the maximum operating speed of the spi is 10mhz. 4.15.2 legacy mode & start-up in legacy mode, basic configuration of the device including a subset of equalizer settings are available at the pin level. in this mode, register settings are automatically set to default so that the ic is live at power-up. 4.15.3 host interface mode & start-up in host interface mode, the user gains access to control and status registers (csrs) that manage advanced features. in this mode, equalizer and de-emphasis settings are set through the csr. the spi control port is functional at start- up without the need for a separate, external reset signal. however, all internal registers mu st be set to their default state by issuing a required reset command via the spi. this is done by setting the r bit (reset) low in the command word. this will guarantee the csr will not start up in a random state. a simple way to issue the required reset of the csr is to hold the slave device?s sdi input low for an entire 64 cycle write communication. details of the write operation are found in section 4.15.6 below. 4.15.4 clock & data timing the spi signals are serial data input (sdi), serial data output (sdo), active-low chip select (cs ), and serial clock input (sck). the host interface operates in spi mode 0, i.e. the sdi input will latch data in on the rising edge of sck. the sdo data output will transition on falling edges of sck. data is transmitted or received on the spi port msb first lsb last. fi g ure 4-4: data c lo c k ali g nment sck cs cycle # 1 2 3 4 5 6 7 8 sdo 1 2 3 4 5 6 7 8 z z 1 2 3 4 5 6 7 8 z z sdi
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 26 of 41 4.15.5 single device operation for applications with a single device or applications with multiple devices where daisy chaining is not desired, the chain position bits c[6:0] should always be set to 0. as a by-product of the daisy chaining feature, read and write operations experience a 32 sck cycle latency from sdi to sdo. for more details on daisy-chaining, refer to section 4.15.8 on page 29 . fi g ure 4-5: 16- b it c omman d format 4.15.6 write operat ion - single device a write operation consists of a 16-bit command word and a 16-bit data word, followed by 32 cycles with the slave sdi held high. when writing to a single non-daisy chained device, the following format should be used: fi g ure 4-6: s in g le devi c e write 1. at power-up, the device should be reset by setting the r bit low. a simple way to accomplish a reset is to hold the slave sdi line low for an entire 64 cycle communication. 2. for a write operation, the r/w bit should be set to 0. 3. the 2nd and 3rd bits are rese rved and should be set to 0. 4. the r bit should always be set high for a normal write operation. 5. refer to the register map for info rmation on address and data bits. 6. the slave sdi line should be held hi gh for 32 cycles before de-asserting cs . rw a[4:0] r 0 0 read/ write reset address c n [ 6 :0] = `0000000? chain position command? [15:0] data [15:0] mosi command [15:0] data high 32 cycles cs rw a[4:0] r 0 0 r/w reset address c[ 6 :0] = 0 chain position 1 6 bit command data [15:0] command [15:0] data [15:0] miso
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 27 of 41 4.15.7 read operation - single device for reading from a device the following format should be used: fi g ure 4-7: s in g le devi c e rea d 1. for a read operation, the r/w bit should be set to 1. 2. the 2nd and 3rd bits are rese rved and should be set to 0. 3. the r bit should always be set high for a normal read operation. 4. data out at the slave sdo will appear after holding the slave sdi line high for 32 cycles. 5. the 16-bit data is now available on the slave sdo line. detailed timing diagrams for write and read can be seen in figure 4-8 and figure 4-9 . mosi miso command [15:0] data [15:0] command? [15:0] data high 1 6 cycles cs rw a[4:0] r 0 0 r/w reset address c[ 6 :0] = 0 chain position 1 6 bit command data high 1 6 cycles data high 1 6 cycles
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 28 of 41 fi g ure 4-8: s pi write timin g fi g ure 4-9: s pi rea d timin g r/w 0 r c0 c1 c2 c3 c4 c5 c 6 a0 a1 a2 a4 a3 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 sck cs sdi 32 cycles delayed sdo t 0 t 3 t 1 t 2 r/w 0 0 c0 c1 c2 c3 c4 c5 c 6 a0 a1 a2 a4 a3 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 t 8 t 7 t 6 0 r r/w 0 0 r c0 c1 c2 c3 c4 c5 c 6 a0 a1 a2 a4 a3 sck cs sdi 32 cycles delayed sdo t 0 t 3 t 1 t 2 c0 c1 c2 c3 c4 c5 c 6 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 t 8 r/w 0 0 r a0 a1 a2 a4 a3 table 4-10: gspi time delay parameter symbol conditions min ty p max units cs _n low b efore ho s t_ c lk risin g e dg et 0 50% levels 1.5 ?? ns ho s t_ c lk perio d t 1 100 ?? ns ho s t_ c lk d uty c y c le t 2 40 50 60 % input d ata setup time t 3 1.5 ?? ns output hol d time (15pf loa d )t 6 1.5 ?? ns cs _n high after last ho s t_ c lk risin g e dg et 7 75% of ho s t_ c lk perio d ?? ns input d ata hol d time t 8 1.5 ?? ns
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 29 of 41 4.15.8 daisy chain operation for applications with multiple gs 2986 devices, it is po ssible to daisy-chai n up to 127 parts in serial. in this configuration, the first device sdi should be connected to the spi master sdo. the serial data output of each device is then connected to the serial data input of the following device, and so on. the last device's sdo connects to the master's sdi. connecting devices in serial reduces the number of i/o ports required by the master by removing the need for additional chip select lines. fi g ure 4-10: daisy c haine d s pi bus the position of each GS2986 device in the serial ch ain is referred to as it s chain position, with 0 corresponding to the first device. the chain position in the spi command word is decoded by each slave to know which device the master is talking to. each GS2986 slave is designed to output a replica of what it receives at its input after a delay of 32 cycles. the chain position part of the command is decremented by one in the duplicated command word at the output. each device in the chain will only execute the issued command if it verifies that the current chain position is set to 0. fi g ure 4-11: c hain position de c o d in g spi master sck sdo sdi cs spi slave sck sdi sdo cs sck sdi sdo cs sck sdi sdo cs spi slave spi slave chain position 0 chain position 1 chain position 2 g s298 6 sdi sdo chain position -1 a[4:0] chain position a[4:0] c[ 6 :0]= n 32 cycles g s298 6 sdi sdo chain position -2 32 cycles c[ 6 :0]= n-1 c[ 6 :0]= n-2 a[4:0]
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 30 of 41 4.15.9 read & write operat ion - daisy chained devices in a serial daisy chain configuration, read and/or write operations can be performed to multiple devices in the chain via consecutive operations. figure 4-12 below shows a simple 3 device configuration. fi g ure 4-12: three devi c es in daisy c hain c onfi g uration 4.15.10 writing to all devices when writing to all devices in the chain, a write command and corresponding data is required for each device. when the devices are being configured in the same way, all of them will have the same command and data with the exception of the chain position bits. this example assumes a 3-device daisy chain. a command is is sued to the last device in the chain first, although it is possible to talk to the devices in any order. fi g ure 4-13: daisy c hain write 1. the first command issued in time is the command for the last device in the chain (chain position = 2). when the first device receives this command it will recognize that the chain position is 2 and will not execute the comman d. it will duplicate the command and data word at its output and decrement the chain position by one. 2. consecutive commands are issued for each device in the chain as shown. g s298 6 sdi sdo g s298 6 sdi sdo g s298 6 sdi sdo mosi c miso data [15:0] command0 [15:0] data [15:0] mosi command2 [15:0] data high 32 cycles chain position = 2 cs data [15:0] command1 [15:0] chain position = 1 chain position = 0 miso data [15:0] command0' [15:0]
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 31 of 41 4.15.11 writing to a single device in the chain the following example shows how to write to a single device in a chain: fi g ure 4-14: daisy c hain write to a s in g le devi c e 1. the command is issued to chain position n. 2. 32xn cycles are required to shift the command through n devices. the device at chain position n executes the command. 3. 32 additional cycles are needed to complete the communication. 4.15.12 reading from all devices to read from all devices in the chain, a read command is issued for each device consecutively. after each command, the data is held high for 16 cycles. once a device recognizes it is being talked to, it will outp ut data from the register requested. clock needs to be applied to cycle the output data through all devices in the chain. fi g ure 4-15: daisy c hain rea d 1. read command is issued to the last device in the chain, followed by read commands to the lower chain positions. 2. clock is applied to cycle the output data through the chain. datan [15:0] mosi commandn [15:0] data high 32xn cycles data high 32 cycles chain position = n cs chain position = n (n = 0 for first device in chain) datan [15:0] commandn? [15:0] miso command 2 command 1 sdi sdo data hi g h for 1 6 cycles command 0 data hi g h for 1 6 cycles data hi g h for 1 6 cycles (chain position = 0) data2 data0 data1 data held hi g h for 32x3 cycles command2? command1? command0? sdi sdo (chain position = 1) (chain position = 2) cs cs
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 32 of 41 3. command2? refers to the altered or decremented command2. 4.15.13 reading from a sing le device in the chain the following example shows how to read from a single device in a chain: fi g ure 4-16: daisy c hain rea d from a s in g le devi c e 1. read command and 16 cycles of data held high are issued to chain position n. 2. 32xn cycles are applied with data high to cycle the command through n devices in the chain (note: n is 0 for first device in chain). device n executes the command. 3. with k representing the total number of devices in the chain, 32x(k-n-1) cycles are applied to bring the return data through the rest of the chain. 4. 16 additional cycles are applied until the data from device n is available on the master sdi. mosi miso commandn [15:0] datan [15:0] commandn? [15:0] data high 1 6 cycles data high 32xn cycles data high 32x(k-n-1) cycles data high 1 6 cycles data high 1 6 cycles chain position = n cs chain position = n (n = 0 for first device in chain) chain length = k (k 1)
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 33 of 41 4.15.14 host register map table 4-11: host register map register name register address bit position access function default value valid range comments eq_1 0x00 15:10 rw reserve d . 9 rw input attenuation ena b le (atten_en) 0x0 0 or 1 ena b le for input si g nals a b ove 1vpp d ifferential 8rwe q ualizer offset c orre c tion ena b le 0x1 0 or 1 re c ommen d always on 7rwe q ualizer gain s ettin g for ddi3 0x0 0 or 1 s ee supplementary ta b le b elow 6rwe q ualizer gain s ettin g for ddi2 0x0 0 or 1 s ee supplementary ta b le b elow 5rwe q ualizer gain s ettin g for ddi1 0x00 0 or 1 s ee supplementary ta b le b elow 4rwe q ualizer gain s ettin g for ddi0 0x00 0 or 1 s ee supplementary ta b le b elow 3rwe q ualizer ena b le for ddi3 0x00 0 or 1 s ee supplementary ta b le b elow 2rwe q ualizer ena b le for ddi2 0x00 0 or 1 s ee supplementary ta b le b elow 1rwe q ualizer ena b le for ddi1 0x00 0 or 1 s ee supplementary ta b le b elow 0rwe q ualizer ena b le for ddi0 0x00 0 or 1 s ee supplementary ta b le b elow equalizer decode logic eq_en eq_gain eq setting recommended trace lengths 0 0 low 0 to 10 in c hes of fr4 0 1 low 0 to 10 in c hes of fr4 1 0 med 10 to 20 in c hes of fr4 1 1 high 20 or more in c hes of fr4
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 34 of 41 driver_1 0x01 15:10 rw unuse d 0x0 0 or 1 ? 9 rw amplitu d e c ontrol for ddo1 0x1 0 or 1 0 = 800mv swin g 1 = 400mv swin g 8 rw amplitu d e c ontrol for ddo0 0x1 0 or 1 0 = 800mv swin g 1 = 400mv swin g 7:5 rw de-emphasis boost amplitu d e c ontrol for ddo1 0x2 0x0 to 0x7 0x0 = lowest s ettin g 0x7 = hi g hest s ettin g 4:2 rw de-emphasis boost amplitu d e c ontrol for ddo0 0x2 0x0 to 0x7 0x0 = lowest s ettin g 0x7 = hi g hest s ettin g 1 rw de-emphasis ena b le for ddo1 0x0 0 or 1 1 = ena b le d 0 = disa b le d 0 rw de-emphasis ena b le for ddo0 0x0 0 or 1 1 = ena b le d 0 = disa b le d top_1 0x02 15:9 rw reserve d . 8:7 rw lo s threshol d a d just 0x0 0x0 to 0x3 0x0 = least sensitive 0x3 = most sensitive 6:5 rw lo s dete c tion metho d s ele c t 0x0 0x0 to 0x2 0x0 = le g a c y e dg e d ete c tion metho d 0x1 = new si g nal stren g th d ete c tion metho d 0x2 = d ual d ete c tion metho d : b oth must say si g nal present for lo s to b e low 4rwlo s mute ena b le 0x0 0 or 1 when ena b le d the output will automati c ally mute if loss of s i g nal is high 3 rw power down 0x0 0 or 1 c hip powers d own when asserte d 2rwtri- s tate ena b le for s pi output 0x0 0 or 1 when ena b le d the s pi s do will b e hi g h z when cs is not sele c te d table 4-11: host register map (continued) register name register address bit position access function default value valid range comments
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 35 of 41 top_1 0x02 1 rw c rystal buffer disa b le 0x0 0 or 1 0 = ena b le d 1 = disa b le d 0 rw data polarity invert 0x0 0 or 1 0 = not inverte d 1 = inverte d 0x03 to 0x0b reserve d . pin_or_1 0x0 c 15:13 rw unuse d 0x0 0 or 1 ? 12 rw data/ c lo c k 0x0 0 or 1 ? 11 rw ddo1_dia s ble 0x0 0 or 1 ? 10 rw data_mute 0x0 0 or 1 ? 9:8 rw kbb 0x0 0x0, 0x2 or 0x3 e q uivalent settin g s: 0x0 = kbb to g roun d 0x2 = kbb floatin g 0x3 = kbb to v cc 7rw ss 10x00 or 1 ? 6rw ss 00x00 or 1 ? 5rwauto/man 0x0 0 or 1 ? 4rwautobypa ss 0x0 0 or 1 ? 3rwbypa ss 0x0 0 or 1 ? 2rwddi_ s el1 0x0 0 or 1 ? 1rwddi_ s el0 0x0 0 or 1 ? 0 rw pin overri d e ena b le 0x0 0 or 1 when ena b le d input values will b e taken from this re g ister instea d of pa c ka g e pins s tatu s _1 0x0d 15:4 ro reserve d . ?? ? 3ro s d/hd ?? ? 2rolo c ked ?? ? 1ro ss 1 ?? ? 0ro ss 0 ?? ? 0x0e to 0x11 reserve d . table 4-11: host register map (continued) register name register address bit position access function default value valid range comments
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 36 of 41 4.16 device power-up in host mode (hif pin tied low), control & status registers (csrs) may start up in a random state. there is a bit in the command word r which will reset the csr when set low. in non-host mode (hif pin tied high), the hif pin is used to trigger an internal reset signal to place all registers in a deterministic, default state upon power-up. in either host mode or non-host mode, other in ternal state machines (e.g. offset correction and pll) automatically recover from any state at st art-up with no reset required. it takes ~10 s for the device to lock after start-up. 4.17 standby the purpose of standby mode is to allow oper ating power to be reduced when the device's functionality is not required, and to have a rapi d and simple transition to full operation when the device is required. in order to achieve this, the device can be powe red-down by writing a ?1? to the ?power down? bit located in regi ster address 0x02.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 37 of 41 5. typical application circuit fi g ure 5-1: g s 2986 typi c al appli c ation c ir c uit 10n ddi0 1 hif 2 ddi0 3 4 ddi1 5 6 ddi1 7 8 ddi2 9 10 ddi2 11 12 ddi3 13 14 ddi3 15 16 ddi_sel0 17 ddi_sel1 18 19 20 21 vcc_vco 22 vee_vco 23 24 25 26 vdd_1p8 27 locked 28 los 29 vdd_dig 30 vss_dig 31 32 vee_ddo0 vcc_ddo0 ddo0 ddo0 vee_ddo1 vcc_ddo1 ddo1/rco 40 39 ddo1/rco 38 37 36 ddo1_disable 35 34 sd/hd 33 cp_cap lf+ vcc_cp vee_cp sdi/eq0_en sdo/eq1_en sck/eq2_en cs/eq3_en xtal- xtal+ GS2986 vcc gnd 10n 10n 27mhz 47n 18p 18p vcc gnd locked 220n 10n los gnd 1u 10u gnd 10n vcc gnd vcc gnd gnd hif data input 1 data input 0 data input 2 data input 3 sd/hd ddo1_disable data output 0 data output 1/ serial clock rsvd ddi_sel0 ddi_sel1 sdi/eq0_en sdo/eq1_en sck/eq2_en cs/eq3_en xtal_buf_out 1m vcc r* 220n gnd note: r* value is set to 2 6 7 for 2.5v supply or 422 for 3.3v supply.
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 38 of 41 6. package and ordering information 6.1 package dimensions
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 39 of 41 6.2 recommended pcb footprint 6.3 packaging data 6 .8 5.1 6 .8 5.1 0.5 4.5 4.5 note: all dimensions are in millimeters. 0.85 5.95 0.25 0.28 parameter value pa c ka g e type 6mm x 6mm 40-pin qfn moisture s ensitivity level 3 jun c tion to c ase thermal resistan c e, j- c 19.9 c /w jun c tion to air thermal resistan c e, j-a (at zero airflow) 34.9 c /w jun c tion to boar d thermal resistan c e, j- b 12.5 c /w psi, 0.5 c /w p b -free an d roh s c ompliant yes
GS2986 multi-rate sdi reclocker with equalization & de-emphasis data sheet 52134 - 3 july 2012 40 of 41 6.4 marking diagram 6.5 solder reflow profile fi g ure 6-1: maximum p b -free s ol d er reflow profile 6.6 ordering information GS2986 xxxxe3 yyww pin 1 id xxxx - last 4 digits (excluding decimal) of sap batch assembly (fin) as listed on packing slip. e3 - pb-free & green indicator yyww - date code 25c 150c 200c 217c 2 6 0c 250c time temperature 8 min. max 6 0-180 sec. max 6 0-150 sec. 20-40 sec. 3c/sec max 6 c/sec max part number package temperature range g s 2986 g s 2986-ine3 p b -free 40-pin qfn -40 c to 85 c g s 2986 g s 2986-inte3 p b -free 40-pin qfn (250p c . tape an d reel) -40 c to 85 c g s 2986 g s 2986-inte3z p b -free 40-pin qfn (2.5k tape an d reel) -40 c to 85 c
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